There have been known movie projectors for displaying a 3D image (which will be referred to hereinbelow as “3D image processing apparatus).
FIG. 1 is a block diagram showing a 3D projector.
In FIG. 1, the 3D projector includes input terminal 101 for receiving the left-eye image signal, input terminal 102 for receiving the right-eye image signal, image input circuit 103 and cinema display circuit 104.
Image input circuit 103 receives the left-eye image signal from input terminal 101 and receives the right-eye image signal from input terminal 102. Here, the frame period of the left-eye image signal and the frame period of the right-eye image signal are the same.
FIG. 2 is a diagram for illustrating the operation of image input circuit 103.
Image input circuit 103 combines one frame of left-eye image signal 201 and one frame of right-eye image signal 201, line by line, alternately to produce one frame of output image signal 203 that is to be output to cinema display circuit 104. In this process, image input circuit 103 makes the frame period of output image signal 203 equal to the frame period of left-eye image signal 201 and the frame period of right-eye image signal 202.
Image input circuit 103 typically has a configuration shown in FIG. 3, including image input circuit 103a for receiving the left-eye image signal, image input circuit 103b for receiving the right-eye image signal, clock generating circuit 103c such as PLL or the like that multiplies frequency by 2, line memories 103d and 103e, circuit 103f for generating output timing, and multiplexer 103g for switching the left-eye image and the right-eye image, line by line.
The image signals for left eye and right eye are once written in line memories 103d and 103e, respectively, and read out therefrom at double the speed of writing, by circuit 103c for doubling the input clock frequency.
The timing signals for input image signals (the left-eye image and the left-eye image), including horizontal and vertical synchronization signals and signals indicating valid image data, are input to output timing generating circuit 103f. 
Output timing generating circuit 103f generates timing signals that, based on the input timing signals, form one frame with as many lines as twice the number of the input vertical lines while keeping the total number of clocks for horizontal fixed at that of the input, and switches one line of the left-eye image and one line of the right-eye image alternately to be output.
In this way, the output frame frequency is set to be the same as the frame frequency of the input and the output line frequency set at double the input line frequency, thereby enabling output of a 3D image.
This scheme, however, requires the frequency of the input signal to cinema display circuit 104 to be set so that the doubled frequency falls within the permissible rate of transmission of cinema display circuit 104. That is, the resolution of the image displayable in 3D and the frequency of the vertical synchronization are limited.
To deal with, this frame memories 103h are generally used so that the left-eye image and the left-eye image are read out from frame memories 103h by way of memory interface circuit 103j at an arbitrary clock frequency generated by output clock generating circuit 103i without depending on the clock frequency of the input image signal, or at the permissible maximum input frequency of cinema display circuit 104, and output timing generating circuit 103f outputs signals so as to adjust the number of horizontal clocks and the number of vertical lines to be equal to the input vertical frequency.